Due to the complexity of current circuit designs, the success of first silicon is trending to less than 50%. More designs rely on silicon debug to catch design errors. To enhance the debug capabilities of large circuits, it is desirable to observe internal signals. Scan chains have been used successfully not only for manufacturing test but also for silicon debug. With traditional scan designs, accessing scan cell values is quite straightforward. Nowadays, to reduce the volume of test data and test time, test compression is commonly used. Many test compaction schemes have been shown to significantly reduce test data volume and test application time without losing test quality. Nonetheless, conventional debug techniques still rely heavily on knowing which scan cells capture failing data so that failure analysis equipment can be used to trace failing signals back to defect locations. In this disclosure, the term “failing scan bits” is used to refer to scan cells having incorrect data right before the unloading of the scan chain data. Due to the cost of failure analysis equipment used for debugging, it is desirable to precisely identify failing scan bits.
Several existing techniques can be used to identify failing scan bits in designs with test compression hardware. A first approach is an algorithmic approach. Commercially available compactors are information lossy. However, according to coding theory, a compactor can identify failing scan bits as long as the number of failing scan bits is less than half of its Hamming distance. Some popular compactors, for example, use a Hamming distance of 3, such as the X-compactor (see, e.g., S. Mitra and K. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction”, Proceedings of International Test Conference, 2002), the I-compactor (see, e.g., J. H. Patel, S. S. Lumetta, S. M. Reddy, “Application of Saluja-Karpovsky compactors to test responses with many unknowns,” Proceedings of VLSI Test Symposium 2003, pp. 107-112), and the convolutional compactor (see, e.g., J. Rajski, J. Tyszer, C. Tang and S. M. Reddy, “Convolutional Compaction of Test Responses”, Proceedings of International Test Conference, 2003). Embodiments of these compactors can identify failing scan bits if there is only one failing scan bit in each compaction. Unfortunately, most design errors cause more than one failing scan bit to appear so that heuristics must be used in order to find the best answer from multiple choices. The probability of finding the right answer can be enhanced by using higher Hamming distance compactors. However, such compactors require more hardware and more output pins, and therefore offer lower test compaction.
A second approach is the bypass approach. Typically, test compression designs offer an uncompressed mode of operation in which the circuit operates as a regular scan design without compression. In uncompressed mode, for example, the design may concatenate all scan chains which go to the same compactor into one chain such that all scan cells can be accessed without using the compactor. In operation, after a failure is detected in compressed mode, designs are reconfigured into the uncompressed mode and retested again with uncompressed test patterns which desirably load the same scan cell values as compressed test patterns. Ensuring that both shift operations exist requires some attention to the design. For example, in order to ensure proper shift operation across two scan chains, sometimes, re-timing latches (also known as lock-up latches) are inserted.
A third approach is the hardware approach. In Khoche et al., “Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics,” Proceedings of International Test Conference 2006, paper 8.1., the modified design shown in FIG. 1 was proposed. In this approach, an extra shift register is inserted to constantly parallel capture the scan output values of all scan chains before they enter the output compactor. Whenever there is a need to observe the values captured in this shift register, a mode called “slice shift” is activated by a single special mode control signal. During slice shift mode, internal shift operations are placed on hold and the data on this special shift register is unloaded through compactor outputs. If the timing is set properly, users can use slice shift mode to identify failing scan bits which contribute to a failure detected at compactor outputs if the compactor has combinational logic only. As mentioned in Khoche et al. and in contrast to the bypass approach, if the ATE can support a match loop properly, slice shift mode can be triggered in real time when the ATE detects a failure such that the failing scan bits can be identified without retesting. However, this real time operation cannot support sequential compactors or pipeline stages inserted either inside the compactor or placed between compactor and output pads. Moreover, this approach requires one extra flip-flop for each internal scan chain and other logic is needed to do slice shifting while holding the internal scan shift.